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FUJITSU SEMICONDUCTOR DATA SHEET
DS07-13703-5E
16-bit Proprietary Microcontroller
CMOS
F2MC-16LX MB90540/G/545/G Series
MB90F543/F549/V540 MB90F543G(S)/F546G(S)/F548G(S)/F549G(S)/549G(S)/V540G MB90543G(S)/547G(S)/548G(S)/F548GL(S)
s DESCRIPTION
The MB90540/545 series with FULL-CAN*1 and FLASH ROM is specially designed for automotive and industrial applications. Its main features are two on board CAN Interfaces (one for MB90V545 series) , which conform to V2.0 Part A and Part B, supporting very flexible message buffer scheme and so offering more functions than a normal full CAN approach. The instruction set by F2MC-16LX CPU core inherits an AT architecture of the F2MC*2 family with additional instruction sets for high-level languages, extended addressing mode, enhanced multiplication/division instructions, and enhanced bit manipulation instructions.The micro controller has a 32-bit accumulator for processing long word data.The MB90540/545 series has peripheral resources of 8/10-bit A/D converters, UART (SCI) , extended I/O serial interfaces, 8/16-bit timer, I/O timer (input capture (ICU) , output compare (OCU) ) . *1 : Controller Area Network (CAN) -License of Robert Bosch GmbH. *2 : F2MC stands for FUJITSU Flexible Microcontroller.
s FEATURES
* Clock Embedded PLL clock multiplication circuit Operating clock (PLL clock) can be selected from : divided-by-2 of oscillation or one to four times the oscillation Minimum instruction execution time : 62.5 ns (operation at oscillation of 4 MHz, four times the oscillation clock) Subsystem Clock : 32 kHz (Continued) 100-pin Plastic QFP 100-pin Plastic LQFP
s PACKAGES
(FPT-100P-M06)
(FPT-100P-M05)
(Continued)
MB90540/540G/545/545G Series
* Instruction set to optimize controller applications Rich data types (bit, byte, word, long word) Rich addressing mode (23 types) Enhanced signed multiplication/division instruction and RETI instruction functions Enhanced precision calculation realized by the 32-bit accumulator * Instruction set designed for high level language (C language) and multi-task operations Adoption of system stack pointer Enhanced pointer indirect instructions Barrel shift instructions * Program patch function (for two address pointers) * Enhanced execution speed : 4-byte Instruction queue * Enhanced interrupt function : 8 levels, 34 factors * Automatic data transmission function independent of CPU operation Extended intelligent I/O service function (EI2OS) * Embedded ROM size and types Mask ROM : 256 Kbytes / 64 Kbytes / 128 Kbytes Flash ROM : 128 Kbytes/256 Kbytes Embedded RAM size : 2 Kbytes/4 Kbytes/6 Kbytes/8 Kbytes (evaluation chip) * Flash ROM Supports automatic programming, Embedded Algorithm TM* Write/Erase/Erase-Suspend/Resume commands A flag indicating completion of the algorithm Hard-wired reset vector available in order to point to a fixed boot sector in Flash Memory Erase can be performed on each block Block protection with external programming voltage * Low-power consumption (stand-by) mode Sleep mode (mode in which CPU operating clock is stopped) Stop mode (mode in which oscillation is stopped) CPU intermittent operation mode Clock mode Hardware stand-by mode * Process 0.5 m CMOS technology * I/O port General-purpose I/O ports : 81 ports * Timer Watchdog timer : 1 channel 8/16-bit PPG timer : 8/16-bit x 4 channels 16-bit re-load timer : 2 channels * 16-bit I/O timer 16-bit free-run timer : 1 channel Input capture : 8 channels Output compare : 4 channels * Extended I/O serial interface : 1 channel * UART 0 With full-duplex double buffer (8-bit length) Clock asynchronized or clock synchronized (with start/stop bit) transmission can be selectively used. (Continued)
2
MB90540/540G/545/545G Series
(Continued) * UART 1 With full-duplex double buffer (8-bit length) Clock asynchronized or clock synchronized serial (extended I/O serial) can be used. * External interrupt circuit (8 channels) A module for starting an extended intelligent I/O service (EI2OS) and generating an external interrupt which is triggered by an external input. * Delayed interrupt generation module Generates an interrupt request for switching tasks. * 8/10-bit A/D converter (8 channels) 8/10-bit resolution can be selectively used. Starting by an external trigger input. Conversion time : 26.3 s * FULL-CAN interfaces MB90540 series : 2 channel MB90545 series : 1 channel Conforming to Version 2.0 Part A and Part B Flexible message buffering (mailbox and FIFO buffering can be mixed) * External bus interface : Maximum address space 16 Mbytes * Package: QFP-100, LQFP-100
* : Embedded Algorithm is a trade mark of Advanced Micro Devices Inc.
3
MB90540/540G/545/545G Series
s PRODUCT LINEUP
Features CPU System clock MB90F543/F549 MB90F543G (S) /F548G (S) MB90F549G (S) /F546G (S) MB90F548GL(S) MB90543G (S) *1 MB90547G (S) *1 MB90548G (S) MB90549G (S) F2MC-16LX CPU On-chip PLL clock multiplier (x1, x2, x3, x4, 1/2 when PLL stop) Minimum instruction exection time : 62.5 ns (4 MHz osc. PLL x 4) Flash memory MB90F543/F543G(S)/ F548G(S) / F548GL(S) : 128 K MB90F549/F549G(S)/ F546G(S) : 256 K MB90F548G(S)/F548GL(S): 4 Kbytes MB90F543/F549/F543G (S) / F549G(S) : 6 Kbytes MB90F546G(S) : 8 Kbytes MB90F543/F549/F543G/ F548G/F549G/F546G/F548GL : Two clocks system MB90F543GS/F548GS/ F549GS/F546GS/F548GLS : One clock system Mask ROM : MB90547G(S): 64 K MB90543G(S)/548G(S): 128 K MB90549G(S): 256 K MB90547G(S): 2 Kbytes MB90548G(S): 4 Kbytes MB90543G(S)/549G(S): 6 Kbytes MB90543G/547G/548G/ 549G : Two clocks system MB90543GS/547GS/ 548GS/549GS : One clock system *5 MB90F543/F549: -40 C to 85 C Other than MB90F543/F549: -40 C to 105 C QFP100, LQFP100 PGA-256 None MB90V540/V540G
ROM
External
RAM
8 Kbytes
Clocks
Two clocks system*2
Operating voltage range Temperature range Package Emulator-specify power supply*3 UART0
Full duplex double buffer Support asynchronous/synchronous (with start/stop bit) transfer Baud rate : 4808/5208/9615/10417/19230/38460/62500/500000 bps (asynchronous) 500 K/1 M/2 Mbps (synchronous) at System clock = 16 MHz Full duplex double buffer Asynchronous (start-stop synchronized) and CLK-synchronous communication Baud rate : 1202/2404/4808/9615/19230/31250/38460/62500 bps (asynchronous) 62.5 K/125 K/250 K/500 K/1 M/2 Mbps (synchronous) at 6, 8, 10, 12, 16 MHz Transfer can be started from MSB or LSB Supports internal clock synchronized transfer and external clock synchronized transfer Supports positive-edge and nagative-edge clock synchronization Baud rate : 31.25 K/62.5 K/125 K/500 K/1 Mbps at System clock = 16 MHz 10-bit or 8-bit resolution 8 input channels Conversion time : 26.3 s (per one channel)
UART1 (SCI)
Serial I/O
A/D Converter
(Continued)
4
MB90540/540G/545/545G Series
(Continued)
Features MB90F543/F549 MB90F543G (S) /F548G (S) MB90F549G (S) /F546G (S) MB90F548GL(S) MB90543G (S) *1 MB90547G (S) *1 MB90548G (S) MB90549G (S) MB90V540 MB90V540G
16-bit Reload Timer (2 channels) 16-bit I/O Timer
Operation clock frequency : fsys/21, fsys/23, fsys/25 (fsys = System clock frequency) Supports External Event Count function Signals an interrupt when overflow Supports Timer Clear when a match with Output Compare (Channel 0) Operation clock freq. : fsys/22, fsys/24, fsys/26, fsys/28 (fsys = System clock freq.)
Signals an interrupt when a match with 16-bit I/O Timer 16-bit Output Compare Four 16-bit compare registers (4 channels) A pair of compare registers can be used to generate an output signal 16-bit Input Capture (8 channels) Rising edge, falling edge or rising & falling edge sensitive Four 16-bit Capture registers Signals an interrupt upon external event Supports 8-bit and 16-bit operation modes Eight 8-bit reload counters Eight 8-bit reload registers for L pulse width Eight 8-bit reload registers for H pulse width A pair of 8-bit reload counters can be configured as one 16-bit reload counter or as 8-bit prescaler plus 8-bit reload counter 4 output pins Operation clock freq. : fsys, fsys/21, fsys/22, fsys/23, fsys/24 or 128 s@fosc = 4 MHz (fsys = System clock frequency, fosc = Oscillation clock frequency) Conforms to CAN Specification Version 2.0 Part A and B Automatic re-transmission in case of error Automatic transmission responding to Remote Frame Prioritized 16 massage buffers for data and ID's supports multipe massages Flexible configuration of acceptance filtering : Full bit compare/Full bit mask/Two partial bit masks Supports up to 1 Mbps Sub-clock for low power operation Can be programmed edge sensitive or level sensitive External access using the selectable 8-bit or 16-bit bus is enabled (external bus mode.) Virtually all external pins can be used as general purpose I/O All push-pull outputs and schmitt trigger inputs Bit-wise programmable as input/output or peripheral signal Sub-clock for 32 kHz Sub clock low power operation Supports automatic programming, Embeded Algorithm TM*4 Write/Erase/Erase-Suspend/Erase-Resume commands A flag indicating completion of the algorithm Number of erase cycles : 10,000 times Data retention time : 10 years Boot block configuration Erase can be performed on each block Block protection by externally programmed voltage
8/16-bit Programmable Pulse Generator (4 channels)
CAN Interface MB90540 series : 2 channels MB90545 series : 1 channel 32 kHz Sub-clock External Interrupt (8 channels) External bus interface I/O Ports
Flash Memory
*1 : Under development *2 : If the one clock system is used, equip X0A and X1A with clocks from the tool side. 5
MB90540/540G/545/545G Series
*3 : It is setting of DIP switch S2 when Emulation pod (MB2145-507) is used.Please refer to the MB2145-507 hardware manual (2.7 Emulator-specific Power Pin) about details. *4 : Embedded Algorithm is a trade mark of Advanced Micro Devices Inc. *5 : OPERATING VOLTAGE RANGE Products Operation guarantee range MB90F543/F549/F543G(S)/F546G(S)/F548G(S)/ MB90549G(S)/F549G(S)/V540/V540G MB90F548GL(S)/543G(S)*1/547G(S)*1/548G(S) 4.5 V to 5.5 V 3.5 V to 5.5 V
6
MB90540/540G/545/545G Series
s PIN ASSIGNMENT
(TOP VIEW)
P17/AD15 P16/AD14 P15/AD13 P14/AD12 P13/AD11 P12/AD10 P11/AD09 P10/AD08 P07/AD07 P06/AD06 P05/AD05 P04/AD04 P03/AD03 P02/AD02 P01/AD01 P00/AD00 VCC X1 X0 VSS P20/A16 P21/A17 P22/A18 P23/A19 P24/A20 P25/A21 P26/A22 P27/A23 P30/ALE P31/RD VSS P32/WRL/WR P33/WRH P34/HRQ P35/HAK P36/RDY P37/CLK P40/SOT0 P41/SCK0 P42/SIN0 P43/SIN1 P44/SCK1 VCC P45/SOT1 P46/SOT2 P47/SCK2 C P50/SIN2 P51/INT4 P52/INT5 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
X0A X1A PA0 RST P97/RX1 P96/TX1 P95/RX0 P94/TX0 P93/INT3 P92/INT2 P91/INT1 P90/INT0 P87/TOT1 P86/TIN1 P85/OUT1 P84/OUT0 P83/PPG3 P82/PPG2 P81/PPG1 P80/PPG0 P77/OUT3/IN7 P76/OUT2/IN6 P75/IN5 P74/IN4 P73/IN3 P72/IN2 P71/IN1 P70/IN0 HST MD2
P53/INT6 P54/INT7 P55/ADTG AVCC AVRH AVRL AVSS P60/AN0 P61/AN1 P62/AN2 P63/AN3 VSS P64/AN4 P65/AN5 P66/AN6 P67/AN7 P56/TIN0 P57/TOT0 MD0 MD1
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
(FPT-100P-M06)
7
MB90540/540G/545/545G Series
(TOP VIEW)
100 P21/A17 99 P20/A16 98 P17/AD15 97 P16/AD14 96 P15/AD13 95 P14/AD12 94 P13/AD11 93 P12/AD10 92 P11/AD09 91 P10/AD08 90 P07/AD07 89 P06/AD06 88 P05/AD05 87 P04/AD04 86 P03/AD03 85 P02/AD02 84 P01/AD01 83 P00/AD00 82 VCC 81 X1 80 X0 79 VSS 78 X0A 77 X1A 76 PA0 P22/A18 P23/A19 P24/A20 P25/A21 P26/A22 P27/A23 P30/ALE P31/RD VSS P32/WRL/WR P33/WRH P34/HRQ P35/HAK P36/RDY P37/CLK P40/SOT0 P41/SCK0 P42/SIN0 P43/SIN1 P44/SCK1 VCC P45/SOT1 P46/SOT2 P47/SCK2 C 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
RST P97/RX1 P96/TX1 P95/RX0 P94/TX0 P93/INT3 P92/INT2 P91/INT1 P90/INT0 P87/TOT1 P86/TIN1 P85/OUT1 P84/OUT0 P83/PPG3 P82/PPG2 P81/PPG1 P80/PPG0 P77/OUT3/IN7 P76/OUT2/IN6 P75/IN5 P74/IN4 P73/IN3 P72/IN2 P71/IN1 P70/IN0
8
P50/SIN2 P51/INT4 P52/INT5 P53/INT6 P54/INT7 P55/ADTG AVCC AVRH AVRL AVSS P60/AN0 P61/AN1 P62/AN2 P63/AN3 VSS P64/AN4 P65/AN5 P66/AN6 P67/AN7 P56/TIN0 P57/TOT0 MD0 MD1 MD2 HST
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
(FPT-100P-M05)
MB90540/540G/545/545G Series
s PIN DESCRIPTION
Pin No. LQFP*2 80 81 78 77 75 50 QFP*1 82 83 80 79 77 52 Pin name X0 X1 X0A X1A RST HST P00 to P07 83 to 90 85 to 92 AD00 to AD07 P10 to P17 91 to 98 93 to 100 AD08 to AD15 I I Circuit type Function
A High speed crystal oscillator input pins (Oscillation) Low speed crystal oscillator input pins. For the one clock system parts, perfom external pull-down processing. A (Oscillation) Low speed crystal oscillator input pins. For the one clock system parts, leave it open. B C External reset request input pin Hardware standby input pin General I/O port with programmable pullup. This function is enabled in the single-chip mode. I/O pins for 8 lower bits of the external address/data bus. This function is enabled when the external bus is enabled. General I/O port with programmable pullup. This function is enabled in the single-chip mode. I/O pins for 8 higher bits of the external address/data bus. This function is enabled when the external bus is enabled. General I/O port with programmable pullup. In external bus mode, this function is valid when the corresponding bits in the external address output control resister (HACR) are set to "1". I 8-bit I/O pins for A16 to A23 at the external address/data bus. In external bus mode, this function is valid when the corresponding bits in the external address output control resister (HACR) are set to "0". General I/O port with programmable pullup. This function is enabled in the single-chip mode. Address latch enable output pin. This function is enabled when the external bus is enabled. General I/O port with programmable pullup. This function is enabled in the single-chip mode. Read strobe output pin for the data bus. This function is enabled when the external bus is enabled. General I/O port with programmable pullup. This function is enabled in the single-chip mode or when the WR/WRL pin output is disabled. I Write strobe output pin for the data bus. This function is enabled when both the external bus and the WR/WRL pin output are enabled. WRL is write-strobe output pin for the lower 8 bits of the data bus in 16-bit access. WR is write-strobe output pin for the 8 bits of the data bus in 8-bit access.
P20 to P27 99 to 6 1 to 8 A16 to A23
P30 7 9 ALE P31 8 10 RD I I
P32 10 12 WRL WR
(Continued)
9
MB90540/540G/545/545G Series
Pin No. LQFP*2 QFP*1
Pin name
Circuit type
Function General I/O port with programmable pullup. This function is enabled in the single-chip mode, external bus 8-bit mode or when WRH pin output is disabled.
P33 11 13 WRH I
Write strobe output pin for the 8 higher bits of the data bus. This function is enabled when the external bus is enabled, when the external bus 16-bit mode is selected, and when the WRH output pin is enabled. General I/O port with programmable pullup. This function is enabled in the single-chip mode or when the hold function is disabled. Hold request input pin. This function is enabled when both the external bus and the hold functions are enabled. General I/O port with programmable pullup. This function is enabled in the single-chip mode or when the hold function is disabled. Hold acknowledge output pin. This function is enabled when both the external bus and the hold functions are enabled. General I/O port with programmable pullup. This function is enabled in the single-chip mode or when the external ready function is disabled. Ready input pin. This function is enabled when both the external bus and the external ready functions are enabled. General I/O port with programmable pullup. This function is enabled in the single-chip mode or when the CLK output is disabled. CLK output pin. This function is enabled when both the external bus and CLK outputs are enabled. General I/O port. This function is enabled when UART0 disables the serial data output. Serial data output pin for UART0. This function is enabled when UART0 enables the serial data output. General I/O port. This function is enabled when UART0 disables serial clock output. Serial clock I/O pin for UART0. This function is enabled when UART0 enables the serial clock output. General I/O port. This function is always enabled. Serial data input pin for UART0. Set the corresponding Port Direction Register to input if this function is used. General I/O port. This function is always enabled. Serial data input pin for UART1. Set the corresponding Port Direction Register to input if this function is used.
P34 12 14 HRQ I
P35 13 15 HAK I
P36 14 16 RDY I
P37 15 17 CLK P40 16 18 SOT0 P41 17 19 SCK0 P42 18 20 SIN0 P43 19 21 SIN1 G G G G H
(Continued)
10
MB90540/540G/545/545G Series
Pin No. LQFP*2 QFP*1
Pin name P44
Circuit type
Function General I/O port. This function is enabled when UART1 disables the clock output. Serial clock pulse I/O pin for UART1. This function is enabled when UART1 enables the serial clock output. General I/O port. This function is enabled when UART1 disables the serial data output. Serial data output pin for UART1. This function is enabled when UART1 enables the serial data output. General I/O port. This function is enabled when the Extended I/O serial interface disables the serial data output.
20
22 SCK1 P45
G
22
24 SOT1 P46
G
23
25 SOT2
G
Serial data output pin for the Extended I/O serial interface. This function is enabled when the Extended I/O serial interface enables the serial data output. General I/O port. This function is enabled when the Extended I/O serial interface disables the clock output.
P47 24 26 SCK2 P50 26 28 SIN2 P51 to P54 27 to 30 29 to 32 INT4 to INT7 P55 31 33 ADTG P60 to P63 36 to 39 38 to 41 AN0 to AN3 P64 to P67 41 to 44 43 to 46 AN4 to AN7 P56 45 47 TIN0 D E E D D D G
Serial clock pulse I/O pin for the Extended I/O serial interface . This function is enabled when the Extended I/O serial interface enables the Serial clock output. General I/O port. This function is always enabled. Serial data input pin for the Extended I/O serial interface . Set the corresponding Port Direction Register to input if this function is used. General I/O port. This function is always enabled. External interrupt request input pins for INT4 to INT7. Set the corresponding Port Direction Register to input if this function is used. General I/O port. This function is always enabled. Trigger input pin for the A/D converter. Set the corresponding Port Direction Register to input if this function is used. General I/O port. This function is enabled when the analog input enable register specifies a port. Analog input pins for the 8/10-bit A/D converter. This function is enabled when the analog input enable register specifies A/D. General I/O port. The function is enabled when the analog input enable register specifies a port. Analog input pins for the 8/10-bit A/D converter. This function is enabled when the analog input enable register specifies A/D. General I/O port. This function is always enabled. Event input pin for the 16-bit reload timers 0. Set the corresponding Port Direction Register to input if this function is used.
(Continued)
11
MB90540/540G/545/545G Series
Pin No. LQFP*2 QFP*1
Pin name P57
Circuit type
Function General I/O port. This function is enabled when the 16-bit reload timers 0 disables the output. Output pin for the 16-bit reload timers 0. This function is enabled when the 16-bit reload timers 0 enables the output. General I/O ports. This function is always enabled. Trigger input pins for input captures ICU0 to ICU5. Set the corresponding Port Direction Register to input if this function is used. General I/O ports. This function is enabled when the OCU disables the waveform output. Event output pins for output compares OCU2 and OCU3. This function is enabled when the OCU enables the waveform output. Trigger input pins for input captures ICU6 and ICU7. Set the corresponding Port Direction Register to input and disable the OCU waveform output if this function is used. General I/O ports. This function is enabled when 8/16-bit PPG disables the waveform output. Output pins for 8/16-bit PPGs. This function is enabled when 8/16-bit PPG enables the waveform output. General I/O ports. This function is enabled when the OCU disables the waveform output.
46
48 TOT0 P70 to P75
D
51 to 56
53 to 58
IN0 to IN5
D
P76 , P77
57 , 58
59 , 60
OUT2 , OUT3
D
IN6 , IN7
P80 to P83 59 , 62 61 to 64 PPG0 to PPG3 P84 , P85 63 , 64 65 , 66 OUT0 , OUT1 P86 65 67 TIN1 D D D
Waveform output pins for output compares OCU0 and OCU1. This function is enabled when the OCU enables the waveform output. General I/O port. This function is always enabled. Input pin for the 16-bit reload timers 1. Set the corresponding Port Direction Register to input if this function is used. General I/O port. This function is enabled when the 16-bit reload timers 0 disables the output. Output pin for the 16-bit reload timers 1.This function is enabled when the 16-bit reload timers 1 enables the output. General I/O port. This function is always enabled. External interrupt request input pins for INT0 to INT3. Set the corresponding Port Direction Register to input if this function is used. General I/O port. This function is enabled when CAN0 disables the output. TX output pin for CAN0. This function is enabled when CAN0 enables the output.
P87 66 68 TOT1 P90 to P93 67 to 70 69 to 72 INT0 to INT3 D D
P94 71 73 TX0 D
(Continued)
12
MB90540/540G/545/545G Series
(Continued) Pin No.
LQFP*2 72 QFP*1 74
Pin name P95 RX0 P96
Circuit type
Function General I/O port. This function is always enabled.
D
RX input pin for CAN0 Interface. When the CAN function is used, output from the other functions must be stopped. General I/O port. This function is enabled when CAN1 disables the output. TX output pin for CAN1. This function is enabled when CAN1 enables the output (only MB90540 series) . General I/O port. This function is always enabled. RX input pin for CAN1 Interface. When the CAN function is used, output from the other functions must be stopped (only MB90540 series) . General I/O port. This function is always enabled. Power supply pin for the A/D Converter. This power supply must be turned on or off while a voltage higher than or equal to AVCC is applied to VCC. Power supply pin for the A/D Converter. External reference voltage input pin for the A/D Converter. This power supply must be turned on or off while a voltage higher than or equal to AVRH is applied to AVCC. External reference voltage input pin for the A/D Converter. Input pins for specifying the operating mode. The pins must be directly connected to VCC or VSS. Input pin for specifying the operating mode. The pin must be directly connected to VCC or VSS. Power supply stabilization capacitor pin. It should be connected externally to an 0.1 F ceramic capacitor. Input pin for power supply (5.0 V) . Input pin for power supply (0.0 V) .
73
75 TX1 P97
D
74
76
RX1 PA0 AVCC
D
76 32
78 34
D Power supply Power supply Power supply Power supply C F Power supply Power supply
35
37
AVSS
33
35
AVRH
34 47 48 49 25 21, 82 9, 40, 79
36 49 50 51 27 23, 84 11, 42, 81
AVRL MD0 MD1 MD2 C VCC VSS
*1 : FPT-100P-M06 *2 : FPT-100P-M05
13
MB90540/540G/545/545G Series
s I/O CIRCUIT TYPE
Circuit type
X1, X1A
Diagram
Remarks * High-speed oscillation feedback resistor : 1 M approx. * Low-speed oscillation feedback resistor : 10 M approx.
X0, X0A
A
Standby control signal
* Hysteresis input * Pull-up resistor : 50 k approx. B
R (Pull-up) R HYS input
* Hysteresis input C
R HYS input
VCC P-ch
* CMOS level output * CMOS Hysteresis input
D
N-ch
R
HYS input
(Continued)
14
MB90540/540G/545/545G Series
Circuit type
Diagram
Remarks * CMOS level output * CMOS Hysteresis input * Analog input
VCC P-ch
N-ch
E
P-ch Analog input N-ch R HYS input
R
HYS input
* Hysteresis input * Pull-down Resistor : 50 k approx. (except FLASH devices)
F
R (Pull-down)
VCC P-ch
* CMOS level output * CMOS Hysteresis input * TTL level input (FLASH devices in FLASH writer mode only)
G
R R T
N-ch
HYS input TTL level input
(Continued)
15
MB90540/540G/545/545G Series
(Continued) Circuit type
Diagram
Remarks * CMOS level output * CMOS Hysteresis input * Programmable pull-up resistor : 50 k approx.
VCC VCC P-ch
CNTL P-ch
H
N-ch
R
HYS input
VCC VCC P-ch
CNTL
P-ch
* CMOS level output * CMOS Hysteresis input * TTL level input (FLASH devices in FLASH writer mode only) * Programmable pullup resistor : 50 k approx.
I
R R T
N-ch
HYS input TTL level input
16
MB90540/540G/545/545G Series
s HANDLING DEVICES
(1) Preventing latch-up CMOS IC chips may suffer latch-up under the following conditions : * A voltage higher than VCC or lower than VSS is applied to an input or output pin. * A voltage higher than the rated voltage is applied between VCC and VSS. * The AVcc power supply is applied before the VCC voltage. Latch-up may increase the power supply current drastically, causing thermal damage to the device. For the same reason, care must also be taken in not allowing the analog power-supply voltage (AVCC, AVRH) to exceed the digital power-supply voltage. (2) Handling unused pins Leaving unused input pins open may result in misbehavior or latch up and possible permanent damage of the device. Therefor they must be pulled up or pulled down through resistors. In this case those resistors should be more than 2 k. Unused bi-directional pins should be set to the output state and can be left open, or the input state with the above described connection. (3) Using external clock To use external clock, drive X0 pin only and leave X1 pin unconnected. Below is a diagram of how to use external clock.
MB90540/545 Series X0 Open X1
(4) Use of the sub-clock Use one clock system parts when the sub-clock is not used. In that case, pull-down the pin X0A and leave the pin X1A open. When using two clock system parts, a 32 kHz oscillator has to be connected to the X0A and X1A pins. (5) Power supply pins (VCC/VSS) In products with multiple VCC or VSS pins, the pins of a same potential are internally connected in the device to avoid abnormal operations including latch-up. However you must connect the pins to an external power and a ground line to lower the electro-magnetic emission level to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total current rating. Make sure to connect VCC and VSS pins via the lowest impedance to power lines. It is recommended to provide a bypass capacitor of around 0.1 F between VCC and VSS pins near the device.
VCC VSS
VCC VSS VCC MB90540/545 Series
VSS
VCC VSS
VSS
VCC
17
MB90540/540G/545/545G Series
(6) Pull-up/down resistors The MB90540/545 Series does not support internal pull-up/down resistors (except Port0 - Port3 : pull-up resistors) . Use external components where needed. (7) Crystal Oscillator Circuit Noises around X0 or X1 pins may be possible causes of abnormal operations. Make sure to provide bypass capacitors via the shortest distances from X0, X1 pins, crystal oscillator (or ceramic resonator) and ground lines, and make sure, to the utmost effort, that lines of oscillation circuits do not cross the lines of other circuits. It is highly recommended to provide a printed circuit board artwork surrounding X0 and X1 pins with a ground area for stabilizing the operation. (8) Turning-on Sequence of Power Supply to A/D Converter and Analog Inputs Make sure to turn on the A/D converter power supply (AVCC, AVRH, AVRL) and analog inputs (AN0 to AN7) after turning-on the digital power supply (VCC) . Turn-off the digital power after turning off the A/D converter supply and analog inputs. In this case, make sure that the voltage does not exceed AVRH or AVCC (turning on/off the analog and digital power supplies simultaneously is acceptable) . (9) Connection of Unused Pins of A/D Converter Connect unused pins of A/D converter to AVCC = VCC, AVSS = AVRH = VSS. (10) N.C. Pin The N.C. (internally connected) pin must be opened for use. (11) Notes on Energization To prevent the internal regulator circuit from malfunctioning, set the voltage rise time during energization at 50 s or more (0.2 V to 2.7 V) .
18
MB90540/540G/545/545G Series
(12) Indeterminate outputs from ports 0 and 1 (MB90F543/F549/V540/V540G only) During oscillation setting time of step-down circuit (during a power-on reset) after the power is turned on, the outputs from ports 0 and 1 become following state. * If RST pin is "H", the outputs become indeterminate. * If RST pin is "L", the outputs become high-impedance. Pay attention to the port output timing shown as follow. * RST pin is "H"
Oscillation setting time*2 Power-on reset*1
VCC (Power-supply pin) PONR (power-on reset) signal RST (external asynchronous reset) signal RST (internal reset) signal Oscillation clock signal KA (internal operation clock A) signal
KB (internal operation clock B) signal PORT (port output) signal
Period of indeterminated
*1 : Power-on reset time : Period of "clock frequency x 217" (Clock frequency of 16 MHz : 8.19 ms) *2 : Oscillation setting time : Period of "clock frequency x 218" (Clock frequency of 16 MHz : 16.38 ms)
19
MB90540/540G/545/545G Series
* RST pin is "L"
Oscillation setting time*2 Power-on reset*1
VCC (Power-supply pin) PONR (power-on reset) signal RST (external asynchronous reset) signal RST (internal reset) signal Oscillation clock signal KA (internal operation clock A) signal
KB (internal operation clock B) signal PORT (port output) signal
High-impedance
*1 : Power-on reset time : Period of "clock frequency x 217" (Clock frequency of 16 MHz : 8.19 ms) *2 : Oscillation setting time : Period of "clock frequency x 218" (Clock frequency of 16 MHz : 16.38 ms) (13) Initialization In the device, there are internal registers which are initialized only by a power-on reset. To initialize these registers, please turn on the power again. (14) Directions of "DIV A, Ri" and "DIVW A, RWi" instructions In the Signed multiplication and division instructions ("DIV A, Ri" and "DIVW A, RWi") , the value of the corresponding bank register (DTB, ADB, USB, SSB) is set in "00H". If the values of the corresponding bank registers (DTB, ADB, USB, SSB) are set to other than "00H", the remainder by the execution result of the instruction is not stored in the register of the instruction operand. (15) Using REALOS The use of EI2OS is not possible with the REALOS real time operating system. (16) Caution on Operations during PLL Clock Mode If the PLL clock mode is selected, the microcontroller attempt to be working with the self-oscillating circuit even when there is no external oscillator or external clock input is stopped. Performance of this operation, however, cannot be guaranteed.
20
MB90540/540G/545/545G Series
s BLOCK DIAGRAM
X0, X1 X0A, X1A RST HST 16-bit I/O Timer 16-bit Input Capture 8 ch. 16-bit Output Compare 4 ch. Clock Controller F2MC 16LX CPU
RAM 2 K/4 K/6 K/8 K
IN0 to IN5 IN6/OUT2, IN7/OUT3 OUT0, OUT1
ROM/Flash 128 K/256 K/ 64K(ROM only)
Prescaler SOT0 SCK0 SIN0 Prescaler SOT1 SCK1 SIN1 Prescaler AD00 to AD15 SOT2 SCK2 SIN2 AVCC AVSS AN0 to AN7 AVRH AVRL ADTG External Interrupt 8 ch. 10-bit A/D Converter 8 ch. External Bus Interface Serial I/O A16 to A23 ALE RD WRL WRH HRQ HAK RDY CLK UART1 (SCI) FMC-16 Bus CAN Controller RX0, RX1 * TX0, TX1 * UART0 8/16-bit PPG 4 ch. PPG0 to PPG3
16-bit Reload Timer 2 ch.
TIN0, TIN1 TOT0, TOT1
INT0 to INT7
* : Only the MB90540 series has two channels
21
MB90540/540G/545/545G Series
s MEMORY MAP
The memory space of the MB90540/545 Series is shown below.
MB90V540 MB90543G(S)*2 MB90V540G/F546G (S) MB90F543/F543G(S) FFFFFFH FFFFFFH ROM ROM (FF bank) (FF bank) FF0000H FF0000H FEFFFFH FEFFFFH ROM ROM (FE bank) (FE bank) FE0000H FE0000H FDFFFFH ROM (FD bank) FD0000H FCFFFFH External ROM (FC bank) FC0000H External 00FFFFH 004000H 003FFFH Peripheral 003900H External 0020FFH 001FF5H ROM correction 001FF0H 0018FFH RAM 6 K RAM 8 K 000100H External 0000BFH 000000H Peripheral 0000BFH 000000H 000100H External Peripheral 0000BFH 000000H 000100H External Peripheral 0000BFH 000000H 0010FFH RAM 4 K 000100H External Peripheral 000000H 000100H 0000BFH Peripheral 0018FFH RAM 6 K 003900H 002000H External ROM (Image of FF bank) 00FFFFH 004000H 003FFFH Peripheral 003900H 002000H External ROM (Image of FF bank) 00FFFFH 004000H 003FFFH Peripheral 003900H 002100H*1 External 002000H ROM (Image of FF bank) 00FFFFH 004000H 003FFFH Peripheral 003900H External MB90548G(S) MB90F548GL(S) MB90F548G (S) FFFFFFH ROM (FF bank) FF0000H FEFFFFH ROM (FE bank) FE0000H
External
MB90F549 MB90547G (S)*2 MB90549G (S) /F549G (S) FFFFFFH FFFFFFH ROM ROM (FF bank) (FF bank) FF0000H FF0000H FEFFFFH ROM (FE bank) FE0000H FDFFFFH ROM (FD bank) External FD0000H FCFFFFH ROM (FC bank) FC0000H External 00FFFFH ROM (Image of FF bank) ROM (Image of FF bank) Peripheral
004000H 003FFFH
0008FFH RAM 2 K External
*1 : 002000H for MB90F549 *2 : Under development
Note : The high-order portion of bank 00 gives the image of the FF bank ROM to make the small model of the C compiler effective. Since the low-order 16 bits address are the same, the table in ROM can be referenced without using the "far" specification in the pointer declaration. For example, an attempt to access 00C000H accesses the value at FFC000H in ROM.The ROM area in bank FF exceeds 48 Kbytes, and its entire image cannot be shown in bank 00.The image between FF4000H and FFFFFFH is visible in bank 00, while the image between FF0000H and FF3FFFH is visible only in bank FF.
22
MB90540/540G/545/545G Series
s I/O MAP
Address 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH to 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H Port 0 direction register Port 1 direction register Port 2 direction register Port 3 direction register Port 4 direction register Port 5 direction register Port 6 direction register Port 7 direction register Port 8 direction register Port 9 direction register Port A direction register Analog Input Enable register Port 0 Pullup control register Port 1 Pullup control register Port 2 Pullup control register Port 3 Pullup control register Serial Mode Control Register 0 Serial Status Register 0 Serial input data register 0/ Serial output data register 0 Rate and data register 0 Register Port 0 data register Port 1 data register Port 2 data register Port 3 data register Port 4 data register Port 5 data register Port 6 data register Port 7 data register Port 8 data register Port 9 data register Port A data register Abbreviation Access Resource name PDR0 PDR1 PDR2 PDR3 PDR4 PDR5 PDR6 PDR7 PDR8 PDR9 PDRA Reserved DDR0 DDR1 DDR2 DDR3 DDR4 DDR5 DDR6 DDR7 DDR8 DDR9 DDRA ADER PUCR0 PUCR1 PUCR2 PUCR3 UMC0 USR0 UIDR0/ UODR0 URD0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W UART0 Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Port 8 Port 9 Port A Port 6, A/D Port 0 Port 1 Port 2 Port 3 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B _ _ _ _ _ _ _0B 1 1 1 1 1 1 1 1B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 1 0 0B 0 0 0 1 0 0 0 0B XXXXXXXXB 0 0 0 0 0 0 0XB R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Port 8 Port 9 Port A Initial value XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB _ _ _ _ _ _ _XB
(Continued)
23
MB90540/540G/545/545G Series
Address 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH 40H 41H 42H 43H 44H 45H 46H
Register Serial mode register 1 Serial control register 1 Serial input data register 1/ Serial output data register 1 Serial status register 1 UART1 prescaler control register Serial Edge select register Serial I/O prescaler Serial mode control register Serial mode control register Serial data register Serial Edge select register External interrupt enable register External interrupt request register External interrupt level register External interrupt level register A/D control status register 0 A/D control status register 1 A/D data register 0 A/D data register 1 PPG0 operation mode control register PPG1 operation mode control register PPG0/1 clock selection register PPG2 operation mode control register PPG3 operation mode control register PPG2/3 Clock Selection Register PPG4 operation mode control register PPG5 operation mode control register PPG4/5 clock selection register PPG6 operation mode control register PPG7 operation mode control register PPG6/7 clock selection register
Abbreviation Access
Resource name
Initial value 0 0 0 0 0 0 0 0B 0 0 0 0 0 1 0 0B
SMR1 SCR1 SIDR1/ SODR1 SSR1 CDCR SES1 Prohibited SCDCR SMCS SMCS SDR SES2 ENIR EIRR ELVR ELVR ADCS0 ADCS1 ADCR0 ADCR1 PPGC0 PPGC1 PPG01 Prohibited PPGC2 PPGC3 PPG23 Prohibited PPGC4 PPGC5 PPG45 Prohibited PPGC6 PPGC7 PPG67
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W A/D Converter External Interrupt Extended I/O Serial Interface UART1
XXXXXXXXB 0 0 0 0 1_0 0B 0_ _ _1 1 1 1B _ _ _ _ _ _ _0B 0_ _ _1 1 1 1B _ _ _ _0 0 0 0B 0 0 0 0 0 0 1 0B XXXXXXXXB _ _ _ _ _ _ _0B 0 0 0 0 0 0 0 0B XXXXXXXXB 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B XXXXXXXXB 0 0 0 0 1 _ XXB 0 _ 0 0 0 _ _ 1B
16-bit Programmable Pulse 0 _ 0 0 0 0 0 1B Generator 0/1
0 0 0 0 0 0 _ _B 0 _ 0 0 0 _ _1B
16-bit Programmable Pulse 0 _ 0 0 0 0 0 1B Generator 2/3
0 0 0 0 0 0 _ _B 0 _ 0 0 0 _ _ 1B
16-bit Programmable Pulse 0 _ 0 0 0 0 0 1B Generator 4/5
0 0 0 0 0 0 _ _B 0 _ 0 0 0 _ _ 1B
16-bit Programmable Pulse 0 _ 0 0 0 0 0 1B Generator 6/7
0 0 0 0 0 0 _ _B
(Continued)
24
MB90540/540G/545/545G Series
Address 47H to 4BH 4CH 4DH 4EH 4FH 50H 51H 52H 53H 54H 55H 56H 57H 58H 59H 5AH 5BH 5CH to 6BH 6CH 6DH 6EH 6FH 70H to 7FH 80H to 8FH 90H to 9DH 9EH 9FH A0H A1H
Register
Abbreviation Access Resource name Prohibited ICS01 ICS23 ICS45 ICS67 TMCSR0 TMCSR0 TMR0/ TMRLR0 TMR0/ TMRLR0 TMCSR1 TMCSR1 TMR1/ TMRLR1 TMR1/ TMRLR1 OCS0 OCS1 OCS2 OCS3 Prohibited TCDT TCDT TCCS ROMM R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W ROM Mirror I/O Timer 16-bit Reload Timer 1 16-bit Reload Timer 0
Initial value
Input capture control status register 0/1 Input capture control status register 2/3 Input capture control status register 4/5 Input capture control status register 6/7
Input Capture 0/1 0 0 0 0 0 0 0 0B Input Capture 2/3 0 0 0 0 0 0 0 0B Input Capture 4/5 0 0 0 0 0 0 0 0B Input Capture 6/7 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B _ _ _ _ 0 0 0 0B XXXXXXXXB XXXXXXXXB 0 0 0 0 0 0 0 0B _ _ _ _ 0 0 0 0B XXXXXXXXB XXXXXXXXB Output Compare 0 0 0 0 _ _ 0 0B 0/1 _ _ _0 0 0 0 0B Output Compare 0 0 0 0 _ _ 0 0B 2/3 _ _ _ 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B _ _ _ _ _ _ _ 1B
Timer control status register 0 Timer control status register 0 Timer register 0/reload register 0 Timer register 0/reload register 0 Timer control status register 1 Timer control status register 1 Timer register 1/reload register 1 Timer register 1/reload register 1
Output compare control status register 0 Output compare control status register 1 Output compare control status register 2 Output compare control status register 3
Timer Data register Timer Data register Timer Control register ROM mirror function selection register
Reserved for CAN 0 Interface. Reserved for CAN 1 Interface. Prohibited Program address detection control status register Delayed interrupt/release register Low-power mode control register Clock selection register PACSR DIRR LPMCR CKSCR R/W R/W R/W R/W Address Match Detection Function Low Power Controller Low Power Controller 0 0 0 0 0 0 0 0B
Delayed Interrupt _ _ _ _ _ _ _ 0B 0 0 0 1 1 0 0 0B 1 1 1 1 1 1 0 0B
(Continued)
25
MB90540/540G/545/545G Series
(Continued) Address
A2H to A4H A5H A6H A7H A8H A9H AAH ABH to ADH AEH AFH B0H B1H B2H B3H B4H B5H B6H B7H B8H B9H BAH BBH BCH BDH BEH BFH C0H to FFH Interrupt control register 00 Interrupt control register 01 Interrupt control register 02 Interrupt control register 03 Interrupt control register 04 Interrupt control register 05 Interrupt control register 06 Interrupt control register 07 Interrupt control register 08 Interrupt control register 09 Interrupt control register 10 Interrupt control register 11 Interrupt control register 12 Interrupt control register 13 Interrupt control register 14 Interrupt control register 15 Flash memory control status register (Flash only, otherwise reserved)
Automatic ready function select register External address output control register
Register
Abbreviation Access Prohibited ARSR HACR ECSR WDTC TBTC WTC Prohibited FMCS Prohibited ICR00 ICR01 ICR02 ICR03 ICR04 ICR05 ICR06 ICR07 ICR08 ICR09 ICR10 ICR11 ICR12 ICR13 ICR14 ICR15 External R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W W W W R/W R/W R/W
Resource name
Initial value 0 0 1 1 _ _ 0 0B
External Memory Access Watchdog Timer Time Base Timer Watch Timer
0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 _B XXXXX 1 1 1B 1 - - 0 0 1 0 0B 1 X 0 0 0 0 0 0B
Bus control signal selection register Watchdog Timer control register Time Base Timer Control register Watch timer control register
Flash Memory
0 0 0 X 0 0 0 0B
0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B Interrupt controller 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B
Address 1FF0H 1FF1H 1FF2H 1FF3H 1FF4H 1FF5H
Register Program address detection register 0 Program address detection register 0 Program address detection register 0 Program address detection register 1 Program address detection register 1 Program address detection register 1
Abbreviation Access PADR0 PADR0 PADR0 PADR1 PADR1 PADR1 R/W R/W R/W R/W R/W R/W
Resource name
Initial value XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB
Address Match Detection Function
(Continued)
26
MB90540/540G/545/545G Series
Address 3900H 3901H 3902H 3903H 3904H 3905H 3906H 3907H 3908H 3909H 390AH 390BH 390CH 390DH 390EH 390FH 3910H to 3917H 3918H 3919H 391AH 391BH 391CH 391DH 391EH 391FH 3920H 3921H 3922H 3923H 3924H 3925H 3926H 3927H
Register Reload L Reload H Reload L Reload H Reload L Reload H Reload L Reload H Reload L Reload H Reload L Reload H Reload L Reload H Reload L Reload H
Abbreviation Access
Resource name
Initial value XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB
PRLL0 PRLH0 PRLL1 PRLH1 PRLL2 PRLH2 PRLL3 PRLH3 PRLL4 PRLH4 PRLL5 PRLH5 PRLL6 PRLH6 PRLL7 PRLH7
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Reserved 16-bit Programmable Pulse Generator 6/7 16-bit Programmable Pulse Generator 4/5 16-bit Programmable Pulse Generator 2/3 16-bit Programmable Pulse Generator 0/1
Input Capture Register 0 Input Capture Register 0 Input Capture Register 1 Input Capture Register 1 Input Capture Register 2 Input Capture Register 2 Input Capture Register 3 Input Capture Register 3 Input Capture Register 4 Input Capture Register 4 Input Capture Register 5 Input Capture Register 5 Input Capture Register 6 Input Capture Register 6 Input Capture Register 7 Input Capture Register 7
IPCP0 IPCP0 IPCP1 IPCP1 IPCP2 IPCP2 IPCP3 IPCP3 IPCP4 IPCP4 IPCP5 IPCP5 IPCP6 IPCP6 IPCP7 IPCP7
R R R R R R R R R R R R R R R R Input Capture 6/7 Input Capture 4/5 Input Capture 2/3 Input Capture 0/1
XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB
(Continued)
27
MB90540/540G/545/545G Series
(Continued) Address
3928H 3929H 392AH 392BH 392CH 392DH 392EH 392FH 3930H to 39FFH 3A00H to 3AFFH 3B00H to 3BFFH 3C00H to 3CFFH 3D00H to 3DFFH 3E00H to 3FFFH * Read/write notation R/W : Reading and writing permitted R : Read-only W : Write-only * Initial value notation 0 : Initial value is "0". 1 : Initial value is "1". X : Initial value is undefined. _ : Initial value is unused.
Register Output Compare Register 0 Output Compare Register 0 Output Compare Register 1 Output Compare Register 1 Output Compare Register 2 Output Compare Register 2 Output Compare Register 3 Output Compare Register 3
Abbreviation Access OCCP0 OCCP0 OCCP1 OCCP1 OCCP2 OCCP2 OCCP3 OCCP3 R/W R/W R/W R/W R/W R/W R/W R/W Reserved
Resource name
Initial value XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB
Output Compare 0/1
Output Compare 2/3
Reserved for CAN 0 Interface. Reserved for CAN 0 Interface. Reserved for CAN 1 Interface. Reserved for CAN 1 Interface. Reserved
Note : Addresses in the range 0000H to 00FFH, which are not listed in the table, are reserved for the primary functions of the MCU. A read access to these reserved addresses results in an "X" reading and any write access should not be performed.
28
MB90540/540G/545/545G Series
s CAN CONTROLLER
The MB90540 series contains two CAN controllers (CAN0 and CAN1) , the MB90545 series contains only one (CAN0) . The Evaluation Chip MB90V540 also has two CAN controllers. The CAN controller has the following features : * Conforms to CAN Specification Version 2.0 Part A and B - Supports transmission/reception in standard frame and extended frame formats * Supports transmission of data frames by receiving remote frames * 16 transmitting/receiving message buffers - 29-bit ID and 8-byte data - Multi-level message buffer configuration * Provides full-bit comparison, full-bit mask, acceptance register 0/acceptance register 1 for each message buffer as ID acceptance mask - Two acceptance mask registers in either standard frame format or extended frame formats * Bit rate programmable from 10 Kbps to 1 Mbps (when input clock is at 16 MHz) List of Control Registers Address CAN0 000070H 000071H 000072H 000073H 000074H 000075H 000076H 000077H 000078H 000079H 00007AH 00007BH 00007CH 00007DH 00007EH 00007FH CAN1 000080H 000081H 000082H 000083H 000084H 000085H 000086H 000087H 000088H 000089H 00008AH 00008BH 00008CH 00008DH 00008EH 00008FH Register Message buffer valid register Transmit request register Transmit cancel register Transmit complete register Receive complete register Remote request receiving register Receive overrun register Receive interrupt enable register Abbreviation BVALR TREQR TCANR TCR RCR RRTRR ROVRR RIER Access R/W R/W W R/W R/W R/W R/W R/W Initial Value 00000000 00000000B 00000000 00000000B 00000000 00000000B 00000000 00000000B 00000000 00000000B 00000000 00000000B 00000000 00000000B 00000000 00000000B
(Continued)
29
MB90540/540G/545/545G Series
(Continued) Address
CAN0 003B00H 003B01H 003B02H 003B03H 003B04H 003B05H 003B06H 003B07H 003B08H 003B09H 003B0AH 003B0BH 003B0CH 003B0DH 003B0EH 003B0FH 003B10H 003B11H 003B12H 003B13H 003B14H 003B15H 003B16H 003B17H 003B18H 003B19H 003B1AH 003B1BH CAN1 003D00H 003D01H 003D02H 003D03H 003D04H 003D05H 003D06H 003D07H 003D08H 003D09H 003D0AH 003D0BH 003D0CH 003D0DH 003D0EH 003D0FH 003D10H 003D11H 003D12H 003D13H 003D14H 003D15H 003D16H 003D17H 003D18H 003D19H 003D1AH 003D1BH Acceptance mask register 1 AMR1 R/W XXXXX--- XXXXXXXXB Acceptance mask register 0 AMR0 R/W XXXXX--- XXXXXXXXB XXXXXXXX XXXXXXXXB Acceptance mask select register AMSR R/W XXXXXXXX XXXXXXXXB XXXXXXXX XXXXXXXXB
Register Control status register Last event indicator register Receive/transmit error counter register Bit timing register IDE register Transmit RTR register Remote frame receive waiting register Transmit request enable register
Abbreviation Access CSR LEIR RTEC BTR IDER TRTRR RFWTR TIER R/W, R R/W R R/W R/W R/W R/W R/W
Initial Value 00---000 0----0-1B -------- 000-0000B 00000000 00000000B -1111111 11111111B XXXXXXXX XXXXXXXXB 00000000 00000000B XXXXXXXX XXXXXXXXB 00000000 00000000B XXXXXXXX XXXXXXXXB
30
MB90540/540G/545/545G Series
List of Message Buffers (ID Registers) Address CAN0 003A00H to 003A1FH 003A20H 003A21H 003A22H 003A23H 003A24H 003A25H 003A26H 003A27H 003A28H 003A29H 003A2AH 003A2BH 003A2CH 003A2DH 003A2EH 003A2FH 003A30H 003A31H 003A32H 003A33H 003A34H 003A35H 003A36H 003A37H 003A38H 003A39H 003A3AH 003A3BH CAN1 003C00H to 003C1FH 003C20H 003C21H 003C22H 003C23H 003C24H 003C25H 003C26H 003C27H 003C28H 003C29H 003C2AH 003C2BH 003C2CH 003C2DH 003C2EH 003C2FH 003C30H 003C31H 003C32H 003C33H 003C34H 003C35H 003C36H 003C37H 003C38H 003C39H 003C3AH 003C3BH ID register 6 IDR6 R/W XXXXX--- XXXXXXXXB ID register 5 IDR5 R/W XXXXX--- XXXXXXXXB XXXXXXXX XXXXXXXXB ID register 4 IDR4 R/W XXXXX--- XXXXXXXXB XXXXXXXX XXXXXXXXB ID register 3 IDR3 R/W XXXXX--- XXXXXXXXB XXXXXXXX XXXXXXXXB ID register 2 IDR2 R/W XXXXX--- XXXXXXXXB XXXXXXXX XXXXXXXXB ID register 1 IDR1 R/W XXXXX--- XXXXXXXXB XXXXXXXX XXXXXXXXB ID register 0 IDR0 R/W XXXXX--- XXXXXXXXB XXXXXXXX XXXXXXXXB Register Abbreviation Access Initial Value XXXXXXXXB to XXXXXXXXB XXXXXXXX XXXXXXXXB
General-purpose RAM
R/W
(Continued)
31
MB90540/540G/545/545G Series
(Continued) Address
CAN0 003A3CH 003A3DH 003A3EH 003A3FH 003A40H 003A41H 003A42H 003A43H 003A44H 003A45H 003A46H 003A47H 003A48H 003A49H 003A4AH 003A4BH 003A4CH 003A4DH 003A4EH 003A4FH 003A50H 003A51H 003A52H 003A53H 003A54H 003A55H 003A56H 003A57H 003A58H 003A59H 003A5AH 003A5BH 003A5CH 003A5DH 003A5EH 003A5FH 32 CAN1 003C3CH 003C3DH 003C3EH 003C3FH 003C40H 003C41H 003C42H 003C43H 003C44H 003C45H 003C46H 003C47H 003C48H 003C49H 003C4AH 003C4BH 003C4CH 003C4DH 003C4EH 003C4FH 003C50H 003C51H 003C52H 003C53H 003C54H 003C55H 003C56H 003C57H 003C58H 003C59H 003C5AH 003C5BH 003C5CH 003C5DH 003C5EH 003C5FH ID register 15 IDR15 R/W XXXXX--- XXXXXXXXB ID register 14 IDR14 R/W XXXXX--- XXXXXXXXB XXXXXXXX XXXXXXXXB ID register 13 IDR13 R/W XXXXX--- XXXXXXXXB XXXXXXXX XXXXXXXXB ID register 12 IDR12 R/W XXXXX--- XXXXXXXXB XXXXXXXX XXXXXXXXB ID register 11 IDR11 R/W XXXXX--- XXXXXXXXB XXXXXXXX XXXXXXXXB ID register 10 IDR10 R/W XXXXX--- XXXXXXXXB XXXXXXXX XXXXXXXXB ID register 9 IDR9 R/W XXXXX--- XXXXXXXXB XXXXXXXX XXXXXXXXB ID register 8 IDR8 R/W XXXXX--- XXXXXXXXB XXXXXXXX XXXXXXXXB ID register 7 IDR7 R/W XXXXX--- XXXXXXXXB XXXXXXXX XXXXXXXXB
Register
Abbreviation Access
Initial Value XXXXXXXX XXXXXXXXB
MB90540/540G/545/545G Series
List of Message Buffers (DLC Registers and Data Registers) Address CAN0 003A60H 003A61H 003A62H 003A63H 003A64H 003A65H 003A66H 003A67H 003A68H 003A69H 003A6AH 003A6BH 003A6CH 003A6DH 003A6EH 003A6FH 003A70H 003A71H 003A72H 003A73H 003A74H 003A75H 003A76H 003A77H 003A78H 003A79H 003A7AH 003A7BH 003A7CH 003A7DH 003A7EH 003A7FH 003A80H to 003A87H CAN1 003C60H 003C61H 003C62H 003C63H 003C64H 003C65H 003C66H 003C67H 003C68H 003C69H 003C6AH 003C6BH 003C6CH 003C6DH 003C6EH 003C6FH 003C70H 003C71H 003C72H 003C73H 003C74H 003C75H 003C76H 003C77H 003C78H 003C79H 003C7AH 003C7BH 003C7CH 003C7DH 003C7EH 003C7FH 003C80H to 003C87H Register DLC register 0 DLC register 1 DLC register 2 DLC register 3 DLC register 4 DLC register 5 DLC register 6 DLC register 7 DLC register 8 DLC register 9 DLC register 10 DLC register 11 DLC register 12 DLC register 13 DLC register 14 DLC register 15 Abbreviation Access DLCR0 DLCR1 DLCR2 DLCR3 DLCR4 DLCR5 DLCR6 DLCR7 DLCR8 DLCR9 DLCR10 DLCR11 DLCR12 DLCR13 DLCR14 DLCR15 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial Value ----XXXXB ----XXXXB ----XXXXB ----XXXXB ----XXXXB ----XXXXB ----XXXXB ----XXXXB ----XXXX ----XXXXB ----XXXXB ----XXXXB ----XXXXB ----XXXXB ----XXXXB ----XXXXB XXXXXXXXB to XXXXXXXXB
Data register 0 (8 bytes)
DTR0
R/W
(Continued)
33
MB90540/540G/545/545G Series
(Continued) Address CAN0 CAN1 003A88H 003C88H to to 003A8FH 003C8FH 003A90H 003C90H to to 003A97H 003C97H 003A98H 003C98H to to 003A9FH 003C9FH 003AA0H 003CA0H to to 003AA7H 003CA7H 003AA8H 003CA8H to to 003AAFH 003CAFH 003AB0H 003CB0H to to 003AB7H 003CB7H 003AB8H 003CB8H to to 003ABFH 003CBFH 003AC0H 003CC0H to to 003AC7H 003CC7H 003AC8H 003CC8H to to 003ACFH 003CCFH 003AD0H 003CD0H to to 003AD7H 003CD7H 003AD8H 003CD8H to to 003ADFH 003CDFH 003AE0H 003CE0H to to 003AE7H 003CE7H 003AE8H 003CE8H to to 003AEFH 003CEFH 003AF0H 003CF0H to to 003AF7H 003CF7H 003AF8H 003CF8H to to 003AFFH 003CFFH
Register
Abbreviation Access
Initial Value XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB
Data register 1 (8 bytes)
DTR1
R/W
Data register 2 (8 bytes)
DTR2
R/W
Data register 3 (8 bytes)
DTR3
R/W
Data register 4 (8 bytes)
DTR4
R/W
Data register 5 (8 bytes)
DTR5
R/W
Data register 6 (8 bytes)
DTR6
R/W
Data register 7 (8 bytes)
DTR7
R/W
Data register 8 (8 bytes)
DTR8
R/W
Data register 9 (8 bytes)
DTR9
R/W
Data register 10 (8 bytes)
DTR10
R/W
Data register 11 (8 bytes)
DTR11
R/W
Data register 12 (8 bytes)
DTR12
R/W
Data register 13 (8 bytes)
DTR13
R/W
Data register 14 (8 bytes)
DTR14
R/W
Data register 15 (8 bytes)
DTR15
R/W
34
MB90540/540G/545/545G Series
s INTERRUPT MAP
Interrupt cause Reset INT9 instruction Exception CAN 0 RX CAN 0 TX/NS CAN 1 RX CAN 1 TX/NS External Interrupt INT0/INT1 Time Base Timer 16-bit Reload Timer 0 8/10-bit A/D Converter I/O Timer External Interrupt INT2/INT3 Serial I/O 8/16-bit PPG 0/1 Input Capture 0 External Interrupt INT4/INT5 Input Capture 1 8/16-bit PPG 2/3 External Interrupt INT6/INT7 Watch Timer 8/16-bit PPG 4/5 Input Capture 2/3 8/16-bit PPG 6/7 Output Compare 0 Output Compare 1 Input Capture 4/5 Output Compare 2/3 - Input Capture 6/7 16-bit Reload Timer 1 UART 0 RX UART 0 TX UART 1 RX UART 1 TX Flash Memory Delayed interrupt EI2OS clear N/A N/A N/A N/A N/A N/A N/A *1 N/A *1 *1 N/A *1 *1 N/A *1 *1 *1 N/A *1 N/A N/A *1 N/A *1 *1 *1 *1 *1 *2 *1 *2 *1 N/A N/A Interrupt vector Number #08 #09 #10 #11 #12 #13 #14 #15 #16 #17 #18 #19 #20 #21 #22 #23 #24 #25 #26 #27 #28 #29 #30 #31 #32 #33 #34 #35 #36 #37 #38 #39 #40 #41 #42 Address FFFFDCH FFFFD8H FFFFD4H FFFFD0H FFFFCCH FFFFC8H FFFFC4H FFFFC0H FFFFBCH FFFFB8H FFFFB4H FFFFB0H FFFFACH FFFFA8H FFFFA4H FFFFA0H FFFF9CH FFFF98H FFFF94H FFFF90H FFFF8CH FFFF88H FFFF84H FFFF80H FFFF7CH FFFF78H FFFF74H FFFF70H FFFF6CH FFFF68H FFFF64H FFFF60H FFFF5CH FFFF58H FFFF54H Interrupt control register Number ICR00 ICR01 ICR02 ICR03 ICR04 ICR05 ICR06 ICR07 ICR08 ICR09 ICR10 ICR11 ICR12 ICR13 ICR14 ICR15 Address 0000B0H 0000B1H 0000B2H 0000B3H 0000B4H 0000B5H 0000B6H 0000B7H 0000B8H 0000B9H 0000BAH 0000BBH 0000BCH 0000BDH 0000BEH 0000BFH 35
MB90540/540G/545/545G Series
*1 : The interrupt request flag is cleared by the EI2OS interrupt clear signal. *2 : The interrupt request flag is cleared by the EI2OS interrupt clear signal. A stop request is available. Note : * N/A : The interrupt request flag is not cleared by the EI2OS interrupt clear signal. * For a peripheral module with two interrupt causes for a single interrupt number, both interrupt request flags are cleared by the EI2OS interrupt clear signal. * At the end of EI2OS, the EI2OS clear signal will be asserted for all the interrupt flags assigned to the same interrupt number. If one interrupt flag starts the EI2OS and in the meantime another interrupt flag is set by a hardware event, the later event is lost because the flag is cleared by the EI2OS clear signal caused by the first event. So it is recommended not to use the EI2OS for this interrupt number. * If EI2OS is enabled, EI2OS is initiated when one of the two interrupt signals in the same interrupt control register (ICR) is asserted. This means that different interrupt sources share the same EI2OS Descriptor which should be unique for each interrupt source. For this reason, when one interrupt source uses the EI2OS, the other interrupt should be disabled.
36
MB90540/540G/545/545G Series
s ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Parameter Symbol VCC AVCC AVRH, AVRL VI VO ICLAMP | ICLAMP | IOL IOLAV IOL IOLAV IOH IOHAV IOH IOHAV PD TA TSTG Value Min VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 - 2.0 -40 -40 -55 Max VSS + 6.0 VSS + 6.0 VSS + 6.0 VSS + 6.0 VSS + 6.0 + 2.0 20 15 4 100 50 -15 -4 -100 -50 500 400 +85 +105 +150 Units V V V V V mA mA mA mA mA mA mA mA mA mA mW mW C C C (VSS = AVSS = 0.0 V) Remarks VCC = AVCC AVCC AVRH/AVRL, AVRH AVRL
Power supply voltage Input voltage Output voltage Maximum clamp current Total maximum clamp current "L" level max output current "L" level avg. output current "L" level max overall output current "L" level avg. overall output current "H" level max output current "H" level avg. output current "H" level max overall output current "H" level avg. overall output current Power consumption Operating temperature Storage temperature
*1 *1 *2 *2 *6 *6 *3 *4 *5 *3 *4 *5
Flash device Mask ROM MB90F543/F549
Other than MB90F543/F549
*1 : AVCC, AVRH, AVRL should not exceed VCC. Also, AVRH, AVRL should not exceed AVCC, and AVRL does not exceed AVRH. *2 : VI and VO should not exceed VCC + 0.3 V. VI should not exceed the specified ratings. However if the maximum current to/from an input is limited by some means with external components, the ICLAMP rating supercedes the VI rating. *3 : The maximum output current is a peak value for a corresponding pin. *4 : Average output current is an average current value observed for a 100 ms period for a corresponding pin. *5 : Total average current is an average current value observed for a 100 ms period for all corresponding pins. *6 : * Applicable to pins : P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P80 to P87, P90 to P97, PA0 * Use within recommended operating conditions. * Use at DC voltage (current) . * The +B signal should always be applied with a limiting resistance placed between the +B signal and the microcontroller. * The value of the limiting resistance should be set so that when the +B signal is applied the input current to the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods. * Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input potential may pass through the protective diode and increase the potential at the VCC pin, and this may affect other devices. * Note that if a +B signal is input when the microcontroller current is off (not fixed at 0 V) , the power supply is provided from the pins, so that incomplete operation may result. * Note that if the +B input is applied during power-on, the power supply is provided from the pins and the resulting supply voltage may not be sufficient to operate the power-on result. (Continued) 37
MB90540/540G/545/545G Series
(Continued) * Care must be taken not to leave the +B input pin open. * Note that analog system input/output pins other than the A/D input pins (LCD drive pins, comparator input pins, etc.) cannot accept +B signal input. * Sample recommended circuits :
* Input/Output Equivalent circuits
Protective diode
VCC
+B input (0 V to 16 V)
Limiting resistance
P-ch
N-ch
R
Note : Average output current = operating current x operating efficiency WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
38
MB90540/540G/545/545G Series
2. Recommended Conditions
Parameter Symbol Min 4.5 Power supply voltage VCC, AVCC Value Typ 5.0 Max 5.5 Units V (VSS = AVSS = 0.0 V) Remarks Under normal operation : Other than MB90F548GL(S)/543G(S)/547G(S)/ 548G(S) Under normal operation : MB90F548GL(S)/543G(S)/547G(S)/ 548G(S) Maintain RAM data in stop mode * MB90F543/F549 Other than MB90F543/F549
3.5 3.0 0.022 -40 -40
5.0 0.1
5.5 5.5 1.0 +85 +105
V V F C C
Smooth capacitor Operating temperature
CS TA
*: Use a ceramic capacitor or a capacitor of better 4. AC characteristics. The bypass capacitor should be greater than this capacitor. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. * C Pin Connection Diagram
C
CS
39
MB90540/540G/545/545G Series
3. DC Characteristics
(MB90F543/F549: VCC = 5.0 V 10%, VSS = AVSS = 0.0 V, TA = -40 C to +85 C) (MB90543G(S)/547G(S)/548G(S)/F548GL(S): VCC = 3.5 V to 5.5 V, VSS = AVSS = 0.0 V, TA = -40 C to +105 C) (Other than MB90F543/F549/543G(S)/547G(S)/548G(S)/F548GL(S): VCC = 5.0 V 10%, VSS = AVSS = 0.0 V, TA = -40 C to +105 C) Value Condition Units Remarks Min Typ Max VCC = 4.5 V, IOH = -4.0 mA VCC = 4.5 V, IOL = 4.0 mA VCC = 5.5 V, VSS < VI < VCC 0.8 VCC 2.0 VCC - 0.3 VCC - 0.3 VSS - 0.3 VCC - 0.5 -5 VCC + 0.3 VCC + 0.3 0.2 VCC 0.8 VCC + 0.3 0.4 5 V V V V V V V V A
Parameter
Symbol
Pin name
CMOS VIHS hysteresis input pin Input H TTL input VIH voltage pin MD input VIHM pin CMOS VILS hysteresis input pin Input L TTL input VIL voltage pin MD input VILM pin Output H All output VOH voltage pins Output L All output VOL voltage pins Input leak cur- IIL rent P00 to P07, P10 to Pull-up P17, resisRUP P20 to tance P27, P30 to P37, RST Pulldown RDO MD2 resisWN tance
25
50
100
k
25
50
100
k
(Continued)
40
MB90540/540G/545/545G Series
(Continued)
(MB90F543/F549: VCC = 5.0 V 10%, VSS = AVSS = 0.0 V, TA = -40 C to +85 C) (MB90543G(S)/547G(S)/548G(S)/F548GL(S): VCC = 3.5 V to 5.5 V, VSS = AVSS = 0.0 V, TA = -40 C to +105 C) (Other than MB90F543/F549/543G(S)/547G(S)/548G(S)/F548GL(S): VCC = 5.0 V 10%, VSS = AVSS = 0.0 V, TA = -40 C to +105 C) Value SymParameter Pin name Condition Units Remarks bol Min Typ Max Internal frequency : 16 MHz, 40 55 mA At normal operating ICC Internal frequency : 16 MHz, At Flash programming/eras 50 70 mA Flash device ing Internal frequency : 16 MHz, ICCS 12 20 mA At sleep mode 300 600 A VCC = 5.0 V 1%, 600 1100 A MB90F548GL (S) only Internal frequency : 2 MHz, ICTS MB90543G(S)/ Power At pseudo timer mode 200 400 A 547G(S)/548(S) only supply VCC current* 400 750 A MB90F548GL only Internal frequency : 8 kHz, 50 100 A Mask ROM ICCL At sub operation, TA = 25 C 150 300 A Flash device Internal frequency : 8 kHz, 15 40 A ICCLS At sub sleep, TA = 25 C Internal frequency : 8 kHz, ICCT 7 25 A At timer mode, TA = 25 C ICCH1 At stop, TA = 25 C 5 20 A At hardware standby mode, ICCH2 50 100 A TA = 25 C Input capacity CIN
Other than AVCC, AVSS, AVRH, AVRL, C, VCC, VSS
5
15
pF
* : The power supply current testing conditions are when using the external clock.
41
MB90540/540G/545/545G Series
4. AC Characteristics
(1) Clock Timing (MB90F543/F549: VCC = 5.0 V10%, VSS = AVSS = 0.0 V, TA = -40 C to +85 C) (MB90543G(S)/547G(S)/548G(S)/F548GL(S): VCC = 3.5 V to 5.5 V, VSS = AVSS = 0.0 V, TA = -40 C to +105 C) (Other than MB90F543/F549/543G(S)/547G(S)/548G(S)/F548GL(S): VCC = 5.0 V 10%, VSS = AVSS = 0.0 V, TA = -40 C to +105 C) Parameter Symbol Pin name Value Min 3 Oscillation frequency fC fCL tCYL tLCYL Input clock pulse width Input clock rise and fall time Machine clock frequency Machine clock cycle time PWH, PWL PWLH, PWLL tCR, tCF fCP fLCP tCP tLCP X0, X1 X0A, X1A X0, X1 X0A, X1A X0 X0A X0 3 62.5 Oscillation cycle time 200 10 1.5 62.5 Typ 32.768 30.5 15.2 8.192 122.1 Max 16 5 333 333 5 16 666 Units Remarks
MHz VCC = 5.0 V10% MHz kHz ns ns s ns s ns Duty ratio is about 30% to 70%. When using external clock VCC = 5.0 V10% VCC<4.5 (MB90F548GL(S)/ 543G(S)/547G(S)/548G(S)) VCC<4.5 (MB90F548GL(S)/ 543G(S)/547G(S)/548G(S))
MHz When using main clock kHz ns s When using sub-clock When using main clock When using sub-clock
* Clock Timing
tCYL
X0
PWH tCF tLCYL PWL tCR
0.8 VCC 0.2 VCC
X0A
PWLH tCF PWLL tCR
0.8 VCC 0.2 VCC
42
MB90540/540G/545/545G Series
* Guaranteed PLL operation range
Guaranteed operation range (Other than MB90F548GL(S)/543G(S)/547G(S)/548G(S)) Guaranteed operation range (MB90F548GL(S)/543G(S)/547G(S)/548G(S)) 5.5
Power supply voltage VCC (V)
4.5
3.5
Guaranteed PLL operation range (MB90F548GL(S)/543G(S)/547G(S)/548G(S)) Guaranteed PLL operation range ( Other than MB90F548GL(S)/543G(S)/547G(S)/548G(S)) 1.5 8 16
Machine clock fCP (MHz)
* External clock frequency and Machine clock frequency
x4 x3 x2 x1
16
Machine clock fCP (MHz)
12 9 8 x1/2 (PLL off)
4
3
4
8
16
External clock fC (MHz)
43
MB90540/540G/545/545G Series
AC characteristics are set to the measured reference voltage values below. * Input signal waveform * Output signal waveform
Hysteresis Input Pin
0.8 VCC 0.2 VCC
Output Pin
2.4 V 0.8 V
TTL Input Pin
2.0 V 0.8 V
44
MB90540/540G/545/545G Series
(2) Clock Output Timing
(MB90F543/F549 : VCC = 5.0 V 10%, VSS = AVSS = 0.0 V, TA = -40 C to +85 C) (MB90543G(S)/547G(S)/548G(S)/F548GL(S): VCC = 3.5 V to 5.5 V, VSS = AVSS = 0.0 V, TA = -40 C to +105 C) (Other than MB90F543/F549/543G(S)/547G(S)/548G(S)/F548GL(S): VCC = 5.0 V 10%, VSS = AVSS = 0.0 V, TA = -40 C to +105 C) Parameter Symbol tCYC tCHCL Pin name CLK Condition VCC = 5 V 10% Value Min 62.5 20 Max Units ns ns Remarks
Cycle time CLK CLK
tCYC tCHCL 2.4 V 0.8 V 2.4 V
CLK
(3) Reset and Hardware Standby Input Timing (MB90F543/F549 : VCC = 5.0 V 10%, VSS = AVSS = 0.0 V, TA = -40 C to +85 C) (MB90543G(S)/547G(S)/548G(S)/F548GL(S): VCC = 3.5 V to 5.5 V, VSS = AVSS = 0.0 V, TA = -40 C to +105 C) (Other than MB90F543/F549/543G(S)/547G(S)/548G(S)/F548GL(S): VCC = 5.0 V 10%, VSS = AVSS = 0.0 V, TA = -40 C to +105 C) Parameter Symbol Pin name Value Min 4 tCP Oscillation time of oscillator + 4 tCP 100 Reset input time tRSTL RST 4 tCP ns Max Units ns ms s Remarks Under normal operation In stop mode In pseudo timer mode (MB90543G (S) /547G (S) / 548G (S) ) In pseudo timer mode (Other than MB90543G (S) / 547G (S) /548G (S) ) In sub-clock mode, sub-sleep mode, timer mode Under normal operation
2 tCP Hardware standby input time tHSTL HST 4 tCP

s ns
Note : "tcp" represents one cycle time of the machine clock. Oscillation time of oscillator is time that amplitude reached the 90%. In the crystal oscillator, the oscillation time is between several ms to tens of ms. In FAR/ceramic oscillator, the oscillation time is between handreds of s to several ms. In the external clock, the oscillation time is 0 ns. Any reset can not fully initialize the Flash Memory if it is performing the automatic algorithm. 45
MB90540/540G/545/545G Series
* In under normal operation, pseudo timer mode, sub-clock mode, sub-sleep mode, timer mode
tRSTL, tHSTL
RST HST
0.2 VCC
0.2 VCC
* In stop mode
tRSTL
RST
0.2 VCC 90% of amplitude 0.2 VCC
X0
Internal operation clock
4 tCP Oscillation time of oscillator Oscillation setting time Instruction execution
Internal reset
46
MB90540/540G/545/545G Series
(4) Power On Reset
(MB90F543/F549 : VCC = 5.0 V 10%, VSS = AVSS = 0.0 V, TA = -40 C to +85 C) (MB90543G(S)/547G(S)/548G(S)/F548GL(S): VCC = 3.5 V to 5.5 V, VSS = AVSS = 0.0 V, TA = -40 C to +105 C) (Other than MB90F543/F549/543G(S)/547G(S)/548G(S)/F548GL(S): VCC = 5.0 V 10%, VSS = AVSS = 0.0 V, TA = -40 C to +105 C) Parameter Symbol tR tOFF Pin name VCC VCC Condition Value Min 0.05 50 Max 30 Units ms ms * Due to repetitive operation Remarks
Power on rise time Power off time
* : VCC must be kept lower than 0.2 V before power-on. Note : * The above values are used for creating a power-on reset. * Some registers in the device are initialized only upon a power-on reset. To initialize these register, turn on the power supply using the above values.
tR
VCC
2.7 V 0.2 V 0.2 V tOFF 0.2 V
Sudden changes in the power supply voltage may cause a power-on reset. To change the power supply voltage while the device is in operation, it is recommended to raise the voltage smoothly to suppress fluctuations as shown below. In this case, change the supply voltage with the PLL clock not used. If the voltage drop is 1 V or fewer per second, however, you can use the PLL clock.
VCC 3.0 V VSS
RAM data being held
It is recommended to keep the rising speed of the supply voltage at 50 mV/ms or slower.
47
MB90540/540G/545/545G Series
(5) Bus Timing (Read)
(MB90F543/F549 : VCC = 4.5 V to 5.5 V, VSS = 0.0 V, TA = -40 C to +85 C) (MB90543G(S)/547G(S)/548G(S)/F548GL(S): VCC = 3.5 V to 5.5 V, VSS = AVSS = 0.0 V, TA = -40 C to +105 C) (Other than MB90F543/F549/543G(S)/547G(S)/548G(S)/F548GL(S): VCC = 5.0 V 10%, VSS = AVSS = 0.0 V, TA = -40 C to +105 C) Parameter Symbol tLHLL Pin name ALE ALE, A16 to A23, AD00 to AD15 ALE, AD00 to AD15 A16 toA23, AD00 to AD15, RD A16 to A23, AD00 to AD15 RD RD, AD00 to AD15 RD, AD00 to AD15 RD, ALE RD, A16 to A23 A16 to A23, AD00 to AD15, CLK RD, CLK ALE, RD Condition Value Min tCP/2 - 20 tCP/2 - 20 Max Units Remarks ns
ALE pulse width
Valid addressALEtime
tAVLL
ns
ALEAddress valid time
tLLAX
tCP/2 - 15 tCP - 15

ns
Valid addressRDtime
tAVRL
ns
Valid addressValid data input RD pulse width RDValid data input RDData hold time RDALEtime RDAddress valid time
tAVDV tRLRH tRLDV tRHDX tRHLH tRHAX
3 tCP/2 - 20 0 tCP/2 - 15 tCP/2 - 10 tCP/2 - 20 tCP/2 - 20 tCP/2 - 15
5 tCP/2 - 60 3 tCP/2 - 60
ns ns ns ns ns ns
Valid addressCLKtime RDCLKtime ALERDtime
tAVCH tRLCH tLLRL
ns ns ns
48
MB90540/540G/545/545G Series
* Bus Timing (Read)
tAVCH 2.4 V tRLCH 2.4 V
CLK
tRHLH 2.4 V 2.4 V tLHLL 0.8 V tRLRH 2.4 V
ALE
RD
2.4 V tAVLL tLLAX tLLRL tAVRL 2.4 V tRLDV tRHAX 2.4 V 0.8 V tAVDV 2.4 V 2.4 V 0.8 VCC 0.2 VCC tRHDX 0.8 VCC 0.8 V
A16 to A23
0.8 V
AD00 to AD15
0.8 V
Address
0.8 V
Read data
0.2 VCC
49
MB90540/540G/545/545G Series
(6) Bus Timing (Write)
(MB90F543/F549 : VCC = 4.5 V to 5.5 V, VSS = 0.0 V, TA = -40 C to +85 C) (MB90543G(S)/547G(S)/548G(S)/F548GL(S): VCC = 3.5 V to 5.5 V, VSS = AVSS = 0.0 V, TA = -40 C to +105 C) (Other than MB90F543/F549/543G(S)/547G(S)/548G(S)/F548GL(S): VCC = 5.0 V 10%, VSS = AVSS = 0.0 V, TA = -40 C to +105 C) Parameter Symbol Pin name A16 to A23 AD00 to AD15, WR WR AD00 to AD15, WR AD00 to AD15, WR A16 to A23, WR WR, ALE WR, CLK Condition Value Min tCP - 15 3 tCP/2 - 20 3 tCP/2 - 20 20 tCP/2 - 10 tCP/2 - 15 tCP/2 - 20 Max Units Remarks
Valid addressWRtime WR pulse width Valid data outputWRtime WRData hold time WRAddress valid time WRALEtime WRCLKtime
tAVWL tWLWH tDVWH tWHDX tWHAX tWHLH tWLCH
ns ns ns ns ns ns ns
* Bus Timing (Write)
tWLCH 2.4 V
CLK
tWHLH 2.4 V
ALE
tAVWL tWLWH 2.4 V 0.8 V
WR (WRL, WRH)
tWHAX 2.4 V 2.4 V 0.8 V tDVWH tWHDX 2.4 V Write data 0.8 V 0.8 V
A16 to A23
0.8 V
AD00 to AD15
2.4 V Address 0.8 V
2.4 V
50
MB90540/540G/545/545G Series
(7) Ready Input Timing
(MB90F543/F549 : VCC = 4.5 V to 5.5 V, VSS = 0.0 V, TA = -40 C to +85 C) (MB90543G(S)/547G(S)/548G(S)/F548GL(S): VCC = 3.5 V to 5.5 V, VSS = AVSS = 0.0 V, TA = -40 C to +105 C) (Other than MB90F543/F549/543G(S)/547G(S)/548G(S)/F548GL(S): VCC = 5.0 V 10%, VSS = AVSS = 0.0 V, TA = -40 C to +105 C) Parameter Symbol tRYHS tRYHH Pin name RDY RDY Condition Value Min 45 0 Max Units ns ns Remarks
RDY setup time RDY hold time
Note : If the RDY setup time is insufficient, use the auto-ready function.
* Ready Input Timing
2.4 V
CLK
ALE
RD/WR
tRYHS
tRYHH
RDY no WAIT is used.
0.8 VCC
0.8 VCC
RDY When WAIT is used (1 cycle).
0.2 VCC
51
MB90540/540G/545/545G Series
(8) Hold Timing
(MB90F543/F549 : VCC = 4.5 V to 5.5 V, VSS = 0.0 V, TA = -40 C to +85 C) (MB90543G(S)/547G(S)/548G(S)/F548GL(S): VCC = 3.5 V to 5.5 V, VSS = AVSS = 0.0 V, TA = -40 C to +105 C) (Other than MB90F543/F549/543G(S)/547G(S)/548G(S)/F548GL(S): VCC = 5.0 V 10%, VSS = AVSS = 0.0 V, TA = -40 C to +105 C) Parameter Symbol tXHAL tHAHV Pin name HAK HAK Condition Value Min 30 tCP Max tCP 2 tCP Units ns ns Remarks
Pin floatingHAKtime HAKtimePin valid time
Note : There is more than 1 cycle from the time HRQ is read to the time the HAK is changed. * Hold Timing
HAK
0.8 V tXHAL tHAHV High impedance 2.4 V 0.8 V 2.4 V
Each pin
2.4 V 0.8 V
(9) UART0/1, Serial I/O Timing
(MB90F543/F549 : VCC = 4.5 V to 5.5 V, VSS = 0.0 V, TA = -40 C to +85 C) (MB90543G(S)/547G(S)/548G(S)/F548GL(S): VCC = 3.5 V to 5.5 V, VSS = AVSS = 0.0 V, TA = -40 C to +105 C) (Other than MB90F543/F549/543G(S)/547G(S)/548G(S)/F548GL(S): VCC = 5.0 V 10%, VSS = AVSS = 0.0 V, TA = -40 C to +105 C) Parameter Symbol tSCYC tSLOV tIVSH tSHIX tSHSL tSLSH tSLOV tIVSH tSHIX Pin name SCK0 to SCK2 SCK0 to SCK2, SOT0 to SOT2 Internal clock operaSCK0 to SCK2, tion output pins are CL = 80 pF + 1 TTL. SIN0 to SIN2 SCK0 to SCK2, SIN0 to SIN2 SCK0 to SCK2 SCK0 to SCK2 SCK0 to SCK2, External clock operSOT0 to SOT2 ation output pins are SCK0 to SCK2, CL = 80 pF + 1 TTL. SIN0 to SIN2 SCK0 to SCK2, SIN0 to SIN2 Condition Value Min 8 tCP -80 100 60 4 tCP 4 tCP 60 60 Max 80 150 Units Remarks ns ns ns ns ns ns ns ns ns
Serial clock cycle time SCKSOT delay time Valid SINSCK SCKValid SIN hold time Serial clock "H" pulse width Serial clock "L" pulse width SCKSOT delay time Valid SINSCK SCKValid SIN hold time
Note : * AC characteristic in CLK synchronized mode. * CL is load capacity value of pins when testing. * For tCP (Machine clock cycle time) , refer to " (1) Clock Timing". 52
MB90540/540G/545/545G Series
* Internal Shift Clock Mode
SCK
0.8 V tSLOV 2.4 V tSCYC 2.4 V 0.8 V
SOT
0.8 V tIVSH 0.8 VCC tSHIX 0.8 VCC 0.2 VCC
SIN
0.2 VCC
* External Shift Clock Mode
SCK
0.2 VCC tSLOV 2.4 V tSLSH 0.2 VCC tSHSL 0.8 VCC 0.8 VCC
SOT
0.8 V tIVSH 0.8 VCC tSHIX 0.8 VCC 0.2 VCC
SIN
0.2 VCC
53
MB90540/540G/545/545G Series
(10) Timer Input Timing
(MB90F543/F549 : VCC = 4.5 V to 5.5 V, VSS = 0.0 V, TA = -40 C to +85 C) (MB90543G(S)/547G(S)/548G(S)/F548GL(S): VCC = 3.5 V to 5.5 V, VSS = AVSS = 0.0 V, TA = -40 C to +105 C) (Other than MB90F543/F549/543G(S)/547G(S)/548G(S)/F548GL(S): VCC = 5.0 V 10%, VSS = AVSS = 0.0 V, TA = -40 C to +105 C) Parameter Symbol tTIWH tTIWL Pin name TIN0, TIN1 IN0 to IN7 Condition Value Min 4 tCP Max Units ns Remarks
Input pulse width
* Timer Input Timing
0.8 VCC
0.8 VCC 0.2 VCC tTIWH tTIWL 0.2 VCC
(11) Timer Output Timing
(MB90F543/F549 : VCC = 4.5 V to 5.5 V, VSS = 0.0 V, TA = -40 C to +85 C) (MB90543G(S)/547G(S)/548G(S)/F548GL(S): VCC = 3.5 V to 5.5 V, VSS = AVSS = 0.0 V, TA = -40 C to +105 C) (Other than MB90F543/F549/543G(S)/547G(S)/548G(S)/F548GL(S): VCC = 5.0 V 10%, VSS = AVSS = 0.0 V, TA = -40 C to +105 C) Parameter Symbol tTO Pin name TOT0 to TOT1, PPG0 to PPG3 Condition Value Min 30 Max Units ns Remarks
CLKTOUT change time
* Timer Output Timing
2.4 V
CLK
TOUT
tTO
2.4 V 0.8 V
54
MB90540/540G/545/545G Series
(12) Trigger Input Timing
(MB90F543/F549 : VCC = 4.5 to 5.5 V, VSS = 0.0 V, TA = -40 C to +85 C) (MB90543G(S)/547G(S)/548G(S)/F548GL(S): VCC = 3.5 V to 5.5 V, VSS = AVSS = 0.0 V, TA = -40 C to +105 C) (Other than MB90F543/F549/543G(S)/547G(S)/548G(S)/F548GL(S): VCC = 5.0 V 10%, VSS = AVSS = 0.0 V, TA = -40 C to +105 C) Parameter Symbol tTRGH tTRGL Pin name INT0 to INT7, ADTG Condition Value Min 5 tCP 1 Max Units ns s Remarks Under nomal operation In stop mode
Input pulse width
* Trigger Input Timing
0.8 VCC
0.8 VCC 0.2 VCC tTRGH tTRGL 0.2 VCC
55
MB90540/540G/545/545G Series
5. A/D Converter
* Electrical Characteristics (Other than MB90F543/F549 : VCC = AVCC = 5.0 V10%, VSS = AVSS = 0.0 V, 3.0 V AVRH - AVRL, TA = -40 C to +105 C) Parameter Resolution Conversion error Nonlinearity error Differential nonlinearity error Zero transition voltage Full scale transition voltage Symbol VOT VFST Pin name AN0 to AN7 AN0 to AN7 Value Min Typ Max 10 5.0 2.5 1.9 Units bit LSB LSB LSB mV mV Internal frequency : 16 MHz Internal frequency : 16 MHz VCC = AVCC = 5.0 V 1% Remarks
(MB90F543/F549 : VCC = AVCC = 5.0 V10%, VSS = AVSS = 0.0 V, 3.0 V AVRH - AVRL, TA = -40 C to +85 C)
AVRL - 3.5 AVRL + 0.5 AVRL + 4.5 LSB LSB LSB AVRH - 6.5 AVRH - 1.5 AVRH + 1.5 LSB LSB LSB 352 tCP
Compare time
ns
Sampling time
IAIN VAIN IA IAH IR IRH
AN0 to AN7 AN0 to AN7 AVRH AVRL AVCC AVCC AVRH AVRH AN0 to AN7
64 tCP -1 AVRL AVRL + 2.7 0
5 400 140
1 AVRH AVCC AVRH - 2.7 5 600 260 5 4
ns A V V V mA A A A A LSB
Analog port input current Analog input voltage range Reference voltage range Power supply current
* Flash device Mask ROM *
Reference voltage supply current Offset between input channels
* : When not using an A/D converter, this is the current (VCC = AVCC = AVRH = 5.0 V) when the CPU is stopped. Note: The functionality of the A/D converter is only guaranteed for VCC = 5.0 V 10 % (also for MB90543G(S)/ 547G (S) /548GL (S) /F548GL (S) ) .
56
MB90540/540G/545/545G Series
* A/D Converter Glossary Resolution : Analog changes that are identifiable with the A/D converter Linearity error : The deviation of the straight line connecting the zero transition point ("00 0000 0000" "00 0000 0001") with the full-scale transition point ("11 1111 1110" "11 1111 1111") from actual conversion characteristics Differential linearity error : The deviation of input voltage needed to change the output code by 1 LSB from the theoretical value Total error : The total error is defined as a difference between the actual value and the theoretical value, which includes zero-transition error/full-scale transition error and linearity error.
Total error 3FF 3FE 3FD Digital output {1 LSB x (N - 1) + 0.5 LSB} Actual conversion Value 0.5 LSB
004 003 002 001 AVRL Analog input
VNT (measured value) Actual conversion characteristics Theoretical characteristics 0.5 LSB AVRH
1 LSB = (Theoretical value)
AVRH - AVRL [V] 1024
VOT (Theoretical value) = AVRL + 0.5 LSB [V] VFST (Theoretical value) = AVRH - 1.5 LSB [V] Total error for digital output N = VNT - {1 LSB x (N - 1) + 0.5 LSB} [LSB] 1 LSB
VNT : Voltage at a transition of digital output from (N - 1) to N
(Continued)
57
MB90540/540G/545/545G Series
(Continued)
Linearity error 3FF 3FE 3FD Digital output Differential linearity error Theorential characteristics N+1 Actual conversion value VFST (measured value) VNT 004 003 002 001 AVRL Analog input Actual conversion characteristics Theoretical characteristics VOT (measured value) AVRH AVRL Analog input AVRH Digital output N
Actual conversion value {1 LSB x (N - 1) + VOT }
N-1
V (N + 1) T (measured value) VNT (measured value)
N-2
Acturel conversion value
Linearity error of digital output N
=
VNT - {1 LSB x (N - 1) + VOT} [LSB] 1 LSB
Differential linearity error V (N + 1) T - VNT = - 1 LSB [LSB] of digital N 1 LSB 1 LSB = VFST - VOT [V] 1022 VOT : Voltage at transition of digital output from "000H" to "001H" VFST : Voltage at transition of digital output from "3FEH" to "3FFH" * Notes on Using A/D Converter Select the output impedance value for the external circuit of analog input according to the following conditions, : * Output impedance values of the external circuit of 15 k or lower are recommended. * When capacitors are connected to external pins, the capacitance of several thousand times the internal capacitor value is recommended to minimized the effect of voltage distribution between the external capacitor and internal capacitor. Note : When the output impedance of the external circuit is too high, the sampling period for analog voltages may not be sufficient (sampling period = 4.00 s @machine clock of 16 MHz) . * Equipment of analog input circuit model
Comparator Analog input 3.2 k Max 30 pF Max
* Error The smaller the | AVRH - AVRL |, the greater the error would become relatively.
58
MB90540/540G/545/545G Series
6. Flash Memory Program/Erase Characteristics
Parameter Sector erase time Condition Value Min TA = + 25 C VCC = 5.0 V 7 10,000 16 3,600 s s cycle Typ 1 5 Chip erase time Max 15 Units s s Remarks Excludes 00H programming prior erasure MB90F543/F543G (S) / F548G (S) /F548GL (S) Excludes 00H programming MB90F549/F549G (S) / prior erasure F546G (S) Excludes system-level overhead
Word (16 bit width) programming time Erase/Program cycle
59
MB90540/540G/545/545G Series
s EXAMPLE CHARACTERISTICS
* "H" level output voltage * "L" level output voltage
VOH - IOH
(VCC = 4.5 V, Ta = +25C) 5 4.5 4 3.5 0.6 3 0.9 0.8 0.7
VOL - IOL
(VCC = 4.5 V,Ta = +25C)
VOH [V]
VOL [V]
0 -2 -4 -6 -8 -10
0.5 0.4 0.3 0.2 0.1 0 0 2 4 6 8 10
2.5 2 1.5 1 0.5 0
IOH [mA]
IOL [mA]
* "H" level input voltage/ "L" level input voltage (Hysterisis inpiut)
Vin - Vcc
(Ta = +25C) 5
4
VIH
Vin [V]
3
VIL
2
1
0 3 3.5 4 4.5 5 5.5 6 6.5
Vcc [V]
60
MB90540/540G/545/545G Series
* Power supply current (MB90549G)
Icc - Vcc
(Ta = +25C) 40 fcp = 16 MHz 35 30 25 fcp = 12 MHz 8 fcp = 10 MHz 10 12
Iccs - Vcc
(Ta = +25C) fcp = 16 MHz
fcp = 12 MHz fcp = 10 MHz fcp = 8 MHz 6
Icc [mA]
fcp = 8 MHz 20 15 fcp = 4 MHz 10 fcp = 2 MHz 5 0 2 3 4 5 6 7
Icc [mA]
4
fcp = 4 MHz fcp = 2 MHz
2
0 2 3 4 5 6 7
Vcc [V]
Vcc [V]
ICTS - VCC
(Ta = +25C) 600 100 90 500 80 400 fcp = 2 MHz 70
ICCL - VCC
(Ta = +25C)
ICTS [A]
300
ICCL [A]
60 50 40
200 30 100 20 10 0 2 3 4 5 6 7 0 2 3 4 5 6 7 fcp = 8 kHz
Vcc [V]
Vcc [V]
61
MB90540/540G/545/545G Series
ICCLS - VCC
(Ta = +25C) 40 35 20 30 25 25
ICCT - VCC
(Ta = +25C)
ICCLS [A]
20 15 fcp = 8 kHz 10
ICCT [A]
15
10
5 5 0 2 3 4 5 6 7 0 2 3 4 5
fcp = 8 kHz
6
7
Vcc [V]
Vcc [V]
ICCH2 - VCC
(hardware standby, Ta = +25 C) 100 90 85 70 20 18 16 14
ICCH1 - VCC
(STOP, Ta = +25 C)
ICCH2 [A]
60 50 40 30 20 10 0 2 3 4 5 6 7
ICCH1 [A]
12 10 8 6 4 2 0 2 3 4 5 6 7
VCC [V]
VCC [V]
62
MB90540/540G/545/545G Series
* Power supply current (MB90F549G)
Icc - Vcc
45 40 35
Iccs - Vcc
(Ta = +25 C) 14 fcp = 16 MHz 12 fcp = 12 MHz fcp = 12 MHz fcp = 10 MHz fcp = 16 MHz (Ta = +25 C)
10
30 fcp = 10 MHz
ICC [mA]
ICC [mA]
25 fcp = 8 MHz 20 15 10 fcp = 2 MHz 5 0 2 3 4 5 6 7
8 fcp = 8 MHz 6 fcp = 4 MHz
fcp = 4 MHz
4
2
fcp = 2 MHz
0 2 3 4 5 6 7
VCC [V]
VCC [V]
ICTS - VCC
600 (Ta = +25 C) 300
ICCL - VCC
(Ta = +25 C)
500 fcp = 2 MHz 400
250
200 fcp = 8 kHz
ICTS [A]
ICCL [A]
300
150
200
100
100
50
0 2 3 4 5 6 7
0 2 3 4 5 6 7
VCC [V]
VCC [V]
63
MB90540/540G/545/545G Series
ICCLS - VCC
(Ta = +25 C) 45 40 35 30 15 20 25
ICCT - VCC
(Ta = +25 C)
ICCLS [A]
25 20 15 10 5 0 2 3 4 5 6 7
ICCT [A]
fcp = 8 MHz
10
fcp = 8 MHz 5
0 2 3 4 5 6 7
VCC [V]
VCC [V]
ICCH2 - VCC
(hardware standby, Ta = +25 C) 100 90 85 70 20 18 16 14
ICCH1 - VCC
(STOP, Ta = +25 C)
ICCH2 [A]
ICCH1 [A]
60 50 40 30 20 10 0 2 3 4 5 6 7
12 10 8 6 4 2 0 2 3 4 5 6 7
VCC [V]
VCC [V]
64
MB90540/540G/545/545G Series
s ORDERING INFORMATION
Part number MB90F543PF MB90F549PF MB90F543GPF MB90F543GSPF MB90F546GPF MB90F546GSPF MB90F548GPF MB90F548GSPF MB90F548GLPF MB90F548GLSPF MB90F549GPF MB90F549GSPF MB90543GPF MB90543GSPF MB90547GPF MB90547GSPF MB90548GPF MB90548GSPF MB90549GPF MB90549GSPF MB90F543PFV MB90F549PFV MB90F543GPFV MB90F543GSPFV MB90F546GPFV MB90F546GSPFV MB90F548GPFV MB90F548GSPFV MB90F548GLSPFV MB90F549GPFV MB90F549GSPFV MB90543GPFV MB90543GSPFV MB90547GSPFV MB90547GSPFV MB90548GPFV MB90548GSPFV MB90549GPFV MB90549GSPFV Package Remarks
100-pin Plastic QFP (FPT-100P-M06)
100-pin Plastic LQFP (FPT-100P-M05)
65
MB90540/540G/545/545G Series
s PACKAGE DIMENSIONS
100-pin Plastic QFP (FPT-100P-M06)
Note: Pins width and pins thickness include plating thickness.
23.900.40(.941.016) 20.000.20(.787.008)
80 51
81
50
0.10(.004) 17.900.40 (.705.016) 14.000.20 (.551.008) INDEX Details of "A" part
100 31
1
30
0.25(.010) +0.35 3.00 -0.20 +.014 .118 -.008 (Mounting height) 0~8 0.170.06 (.007.002) 0.800.20 (.031.008) 0.880.15 (.035.006) 0.250.20 (.010.008) (Stand off)
0.65(.026)
0.320.05 (.013.002)
0.13(.005)
M
"A"
C
2001 FUJITSU LIMITED F100008S-c-4-4
Dimensions in mm (inches)
100-pin Plastic LQFP (FPT-100P-M05)
16.000.20(.630.008)SQ 14.000.10(.551.004)SQ
75 51
Pins width and pins thickness include plating thickness.
76
50
0.08(.003) Details of "A" part
INDEX
1.50 -0.10 .059 -.004 (Mounting height)
26
+0.20
+.008
100
0.100.10 (.004.004) (Stand off) 0.25(.010)
0~8 "A" 0.500.20 (.020.008) 0.600.15 (.024.006)
1
25
0.50(.020)
0.200.05 (.008.002)
0.08(.003)
M
0.1450.055 (.0057.0022)
C
2000 FUJITSU LIMITED F100007S-3c-5
Dimensions in mm (inches) 66
MB90540/540G/545/545G Series
FUJITSU LIMITED
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan.
F0207 (c) FUJITSU LIMITED Printed in Japan

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